This invention relates to a serial transmission apparatus of a clock-synchronous type. Such a serial transmission apparatus is responsive to a serial datum represented by a predetermined number of data bits which are transmitted in series.
In the manner which will be described in the following, a conventional serial transmission apparatus comprises a shift register and a data processing circuit. The shift register has a predetermined bit length and is for memorizing the serial datum as a memorized datum within the predetermined bit length. The processing circuit is for processing the memorized datum in response to an interruption request signal which will later be described.
When the serial transmission apparatus receives the serial datum that is transmitted from another serial transmission apparatus, the shift register carries out a first predetermined operation to memorize the serial datum as the memorized datum. When the serial datum is memorized in the shift register so that the data bits have a number corresponding to the predetermined bit length, the data processing circuit processes the memorized datum as a parallel datum known in the art. After that, the shift register carries out the first predetermined operation again.
In this connection, description will be directed to a particular case where the serial transmission apparatus transmits the serial datum towards the other serial transmission apparatus. In the particular case, the data processing circuit forwards the parallel datum to the shift register. After memorized with the parallel datum as the memorized datum, the shift register carries out a second predetermined operation to send out the memorized datum as the serial datum. When the shift register becomes idle, the data processing circuit forwards the parallel datum to the shift register. After that, the shift register carries out the second predetermined operation again.
In the manner which will be described in the following, the serial transmission system further comprises a clock producing circuit, a counter, and a signal producing circuit. The pulse producing circuit is for producing serial clocks in the manner known in the art. The counter is for counting up a counted value in accordance with each of the serial clocks to produce an overflow signal when the counted value becomes equal to a predetermined count value which corresponds to the predetermined bit length. The signal producing circuit is for producing the above-mentioned interruption request signal in response to the overflow signal.
It is assumed here that production of the serial clocks is stopped before the counted value becomes equal to the predetermined count value in a specific case where the serial datum has a data bit length less than the predetermined bit length of the shift register. When the production of the serial clocks is stopped, the counter does not produce the overflow signal even when the serial datum is completely memorized as the memorized datum in the shift register. As a result, the signal producing circuit does not produce the interruption request signal in the specific case as will later be described with reference to the figure. Therefore, the data processing circuit does not process the memorized datum.